A synchronous semiconductor device may generate a plurality of data corresponding to a burst length. To realize it, in general, each of column selection lines in the memory device is activated and then inactivated. Column selection line (CSL) disabling circuits are provided in the synchronous semiconductor device, particularly in respective banks of the memory cell array so as to disable a selected CSL when read/write operation associated with the line is completed. So, whenever a column address is changed, CSLs to be addressed in accordance with column selection-information are activated after all the CSLs in an arbitrary bank are precharged. In case of using the above-mentioned scheme, a large amount of current is consumed during the operation of the device because all the column selection lines are precharged.
A prior art solution to this problem is seen in FIG. 5. A memory cell array 100 is divided into multiple banks (BANK1, BANK2). The column selection lines in a bank are divided to address a plurality of blocks BLK1, BLK2, and CSL disabling circuits are provided for the blocks, respectively. The row component of an external address XA is input in row buffer 110, and then to row decoder 120. Column address information is input into column buffer 30, and from there as CA' into column predecoder 40, where it is predecoded into DCA'. A block-specific component of the column address information DCA.sub.-- BLK' is then assigned to a corresponding CSL disabling circuit 50. Accordingly, only the column selection lines in a block selected by signal CSL' are precharged. As a result, current consumption is reduced during the precharge operation.
In the conventional memory device, the CSL disabling circuit 50 receives a first address DCA.sub.-- BANK' from the column address buffer 30 and the second address DCA.sub.-- BLK' from the column predecoder 40, respectively. The first address, as bank selection-information, is used to select one of banks in the memory cell array. The second address, as block selection-information, is used to select one of blocks in the addressed bank.
Also, in response to the first and second addresses, the CSL disabling circuit generates a CSL line disable signal PCSLD' for disabling a selected CSL' for Nth cycle (N is an integer) of an internal clock signal PCLK from the timing register, before a CSL' to be selected during (N+1)th cycle of the internal clock signal PCLK is enabled. After disabling an enabled CSL' during Nth cycle of the internal clock signal PCLK, the column decoder selects a CSL' which is associated with the third address from the column predecoder during (N+1)th cycle of the internal clock signal PCLK.
As described above, however, the CSL disabling circuit 50 receives the first and second addresses and generates the signal PCSLD' synchronized with the internal clock signal PCLK. Since the first and second addresses are coded as logic signal, i.e. the CSL line disable signal PCSLD', the CSL disabling circuit will have a complicated configuration. Also, the bus lines for the first and second addresses related to each block may increase in number. These may cause a process time for generating the CSL line disable signal PCSLD' and the device size to be increased. Furthermore, there may be overlapped signals on each of the two CSLs which are activated and inactivated at Nth cycle and (N+1)th cycle of the internal clock signal PCLK, respectively, thereby lowering the reliability of the synchronous semiconductor memory device.